THEIS Thomas Future Nanoelectronics
<p>Jun 06, 2011 09:26 PM  (this was 3 years ago)
this talk was part of a conference prob. at google
 
THOMAS THEIS  Direc of Phys Sci at IBM T J Watson Resch Center
 
how do we implement right error correction at correct levels
(as things we small, will have incr variation in the devices)...
 
industry doing new litho generation every 2 years or better;   EUV is crucial...
 
topics:   extension of silicon CMOS tech
 
search for the ultimate FET
 
prospects for ADIABATIC switching and reversible logic  (real change from what we do today);
 
5:20 Moore's Law is in good shape... no slow down evident in density of devices
 
he predicts... will increase exponentially for another 10 years...
 
still, we r approaching some limits...
resistive losses in quiescent states;  thermionic emission loses;
 
real issue is allowable power dissipation...  electric bill to cool and run the servers for 2 years = the cost of the servers;
 
gating close to limits  as gate length drops
(electric bill at server farms is =  to all servers in 2-3 years)
as gate length shrinks... big economic constraints on power dissipation;
 
big change  8:15  in 2004;  cannot buy 7-8 ghz cpu;
if they could do it, they would... cannot do it;
 
gate oxide is not scaling;
 
there is a work around  9:50...  replace 1 nano think... with  hafnium;
 
The solution:  high-k / metal gate...   extendable to 22 nm and beyond...
will produce big reducs in passive power
 
prob this talk was given in 2008...    
he said FinFET was predicted confident. by Intel execs in 2008.
 
The quest for the ultimate FET...
 
he shows a great carbon nanotube device from there Swiss lab... vertical semiconduc FET...
 
sl:  5 nano gate  from carbon nantube
 
sl:  promise of carbon nanotubes:   could get 950 Ghz switching for a 50 nm channel.
 
go to wire-like geometry;   narrow channel, wire like device... carbon nanotubes;
 
vertical nanowire FET  made of carbon NT... made at their Zurich lab;
 
sl  future direction in nantube...  CNT = carbon nanotubes  harvest growth  then suspend them and
wrap a gate around them with CVP;
 
grow a 5 nano wire and wrap a gate all around it;    carbon NT... ultimate provided by nature;
estimate that you might get 950 Ghz  but cannot build it ;
 
sl   dual-gate CNTFET   great nonlinearity of gate to get strong control of current in the channel;
 
ferroelectric...
 
ultra-thin chnalle and wrap-around gate structure;  wrap around gate  on a single NTube;
 
but  FETs will approach the kT limit
 
23:30  FETs  approaching kT limit...
 
Bob Keyes  (emeritus at IBM REs)  keeps track of data:  energy used per clock cycle in a computation
he shows energy dropping on a line... 
limit is the energy stored in the device - the ambient thermal noise... cannot compue beyond that limit...
must store 30 kT  (say) to computer reliably;;
 
What do u do when u hit the wall of thermal noise;
 
minute 26
 
Can we operate FETs near or below the kT limit...
(u could use refrigeration... but it is not efficient... must add cost of fridge + device);
total power has to go down (including refrigeration)
 
2 paths: 1)  conventional  abrupt method  E = 1/2 CV2
 
2)  reversible logic  (do it slowly)  
if willing to do things slowly then u can do things with minimal energy (or no energy)
 
Adiabatic omputing...  50% raise their hands...  change it abruptly with lots of energy or
conserve the energy...   abrupt method is a square wave...
 
quasi static... if willing to do things slowly... have been built and tested...  Dave Frank is an expert (IBM research)
 
have a sinusoidal clock instead of a square wave clock.
 
reversible pipeline  reversible logic...
 
retractile cascade,  reversible pipeline logic...  explored in the 1990s
 
High Q distrib clock is hard to build;
 
to make this work, the clock needs to be really really slow like 1000X as slow;
 
why not commercial?  just do this by lowering clock speed and lower voltage BUT
 
but look at work of Dave J Frank  eg at MIT Workshop on Reversible Computation Feb 14 2005
superconductivity is the answer  (only need to reduce speed by 10X);
 
can get 1 over time3, with superconductor... depends on device physics.
 
George Bourianoff  The Future of Nanocomputing  IEEE Computer 36 pp44-53...
 
new state vectors  (rather than using charge)  Nanoelectronic Initiative...
new devices with difft. state vectors is repres bits;
use spin vectors or electric fields...
electric fields
use computational state vector other than electronic charge
 
magnetic systems:  spins are decoupled environment...  
they WANT to be oscillators... they r high Q systems;
nanoscale  oscillators have been fabricated;
device just wants to sit there and oscillate;
 
how wud we build a new device that is good for reversible logic...;
 
what people r talking abt is doing 10 or 20 or 50  logic steps seq.   before reading it out...
which inevitably causes energy dissipation...;  no one is talking about building a computer
is fully reversible... but rather... do 2, or 10 or 100 logic steps before reading it out... but quite difficult;
 
he is v optimistic that it will happen but not in 5 yrs... that's for sure...
 
short channel device helps... reduces  gate capacitance... also  get  better ballisticity  (better current)
 
as FINFET  gets smaller, it will force us to reduce the voltage, which will reduce the clock speed;
 
assumption with future finfet... is that  as we drop realy small, we will use massive parallelism to 
make up for a REDUCTION in clockspeed.
 
 
 
 
 
1)  conventional logic
 
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