WATTS, Michael, Microphotonic Circuits, MIT, Sept 22, 2014
<p class="MsoNormal" >WATTS, Michael, Microphotonic Circuits, MIT, Sept 22, 2014</p>
<p>
this is a 4:15PM seminar (the first of the academic year) in rm 232 Spilker at Stfd.
This is in the Optics and Electronics Seminar.</p>
<p>
Michael R Watts is a Prof at MIT at the RLE (and a former mgr at Sandia.)
He is introduced by Prof. Olav Solgaard.
His abstract appears below.
The development of large-scale integrated (LSI) circuits in the 1970s led to a revolution in
microelectronics with the development of the microprocessor that revolutionized the world of
computing and computer science, ultimately resulting in the Internet based world we live in
today. Recent developments in microphotonics point to a similar revolution taking place in
today in the development of large-scale integrated (LSI) microphotonic circuits.
Microphotonic circuits can dramatically alleviate communication bottlenecks, reduce power
consumption, enable high-frequency high-fidelity filtering, new sensor modalities, precision
timing, and the direct generation of high-frequency electromagnetic fields in chip-scale
CMOS compatible solutions. Already, breakthroughs in microphotonic circuits have led to
the ability to freely manipulate polarization states on-chip enabling the first demonstration of
a polarization independent microphotonic circuit, the ability to detect infrared radiation
approaching fundamental noise limits, transmit optical data with a one-hundred-fold
reduction in power consumption relative to electrical communications, and route optical data
at nanosecond switching speeds on a silicon chip for the first time. In this talk, we present on
recent developments in microphotonic devices and circuits, including a one-femtojoule-per-bit
silicon modulator, nanophotonic phased arrays that not only enable arbitrary pattern formation
but represent the first large-scale integrated (LSI) microphotonic circuit integrated within a
300mm silicon photonics platform.
*</p>
<p>
1st transistor was in 1947...</p>
<p>
10K transistors = xsistor on first IC in early 1970s.</p>
<p>
now 5B xsistors on latest Intel proc.</p>
<p>
focal plane array imagers have 100M pixels on largest focal plane array.</p>
<p>
10M elements on a 4K (tv) display.</p>
<p>
all have a unit cell with certain characteristics:</p>
<p>
must have strong application drive (cameras, tv, computers) to warrant production costs;
must have low power, etc.</p>
<p>
late 90s... high refrac index...enabled a tightly confined mode...
could get a bend of 2 microns... for the first time, could do really sharp bends.
(dropped the size from 2 cm down to 2 microns!)</p>
<p>
hence, could wrap light around a ring to get a resonance...</p>
<p>
and could cascade them to get a filter response...
to get wave-length division multiplex and could integr with CMOS.</p>
<p>
can we simulate these components accurately?...</p>
<p>
we can use finite diff- td... in transfer design matrix. to sim performance.</p>
<p>
we could produce these using e-beam litho...</p>
<p>
compares design to expt... exclt agreement... get v sharp filter...</p>
<p>
polarization splitter-rotator...</p>
<p>
put TE and TM (transverse electric / magnetic fields) light in and separate them ...</p>
<p>
can split and rotate polarization... (all on-chip)</p>
<p>
30 layers to produce the cmos... then on top put wafer bonded photonics on top...
connect with vias...</p>
<p>
CADENCE.. all 55 cmos, photonic and 3d via layers...</p>
<p>
want to sim this device: use Verilog A...</p>
<p>
CW (continous wave) laser to modulator then to filter and to a receiver (germanium) (all on-chip)</p>
<p>
move away from e-beam fab.. now using immersion litho...
can get sub 100 nm devices using simple masks.</p>
<p>
low power modulators with pn junctions...</p>
<p>
pn is simple to implement... just inject (or deplete) junctions to change refrac index.</p>
<p>
this uses the free carrier plama dispersion effect...</p>
<p>
pros: can inject arbit amt of carriers.</p>
<p>
to make modulators...</p>
<p>
get a data rate of 1.5 Gb/sec...</p>
<p>
v low power silicon modulator (THE lowest!)...
this is the key bottleneck (the modulator)</p>
<p>
CV/ volume c = capacitance. and V is voltage = delta Q over volume...</p>
<p>
need big capacitance per unit volume.</p>
<p>
we want a vertical junction device to get big capacitance and can then get
tighter confinement...</p>
<p>
devel these in 2008...v low loss....</p>
<p>
we dropped power down to 60 femto joules per bit....</p>
<p>
then changed design... just deplete outer micron of ring...
and can get power down to 3 fJ per bit.</p>
<p>
Energy of switching = CV2.</p>
<p>
we then switched fabs from Sandia to Albany (300 mm fab)</p>
<p>
could get full on/off extinction... get up to 25 Gb/sec data rate</p>
<p>
this is in paper by Timurdogen in Nat Communic 2014.</p>
<p>
compared to Sandia results...</p>
<p>
have 3x greater freq shift...</p>
<p>
should be able to get to 38 Ghz freq shift...</p>
<p>
so, what's the applic... perhaps at data centers!!!!</p>
<p>
which are massive...</p>
<p>
4 terabits per sec coming into each processor...</p>
<p>
scaling to 4 Tb/sec... but will not push scaling to limits.</p>
<p>
how abt on-chip networks? (will u replace metal wires? prob not)</p>
<p>
wired communic on chip</p>
<p>
can get 100 watts power consump at 8 nm node....</p>
<p>
but u need 200,000 components to get the same amt of communic...</p>
<p>
need WDM filters.</p>
<p>
how to make electrical contact with the rings....</p>
<p>
adiabatic bend... can have lossless transition... it works!</p>
<p>
can get Qs of 104 or 5.</p>
<p>
can get integrated heaters (for tuning)</p>
<p>
and use temperature sensors (ntegr with the devices)...</p>
<p>
can we do it electro-optically...</p>
<p>
also need low power lasers.</p>
<p>
use silicon nitride wavelengths....</p>
<p>
pump with single 980 nm off chip pump....</p>
<p>
at 1600 nm lambda.</p>
<p>
cooling power needed for lasers is what dominates the energy efficiency of lasers....</p>
<p>
and finallly... receivers...</p>
<p>
need low capac interconnects...</p>
<p>
want to direct integrate with CMOS...</p>
<p>
do flip chip direct bonding and then drill vias.</p>
<p>
at 8 nm we want to get to 25 fJ per bit including electronics.</p>
<p>
want to get 100 watts for entire device</p>
<p>
limits: laser power and sensitivity...</p>
<p>
will communic drive the market for these devices (yes)
but will communic also drive the future scaling? (he is not sure)</p>
<p>
phased arrays... change phase of arrays to steer it...</p>
<p>
shows unit cell that is 9 microns... includes heater...</p>
<p>
shows active optical phased array demo...</p>
<p>
shows video...of beamsplitting and mvmt os spots of lights vert and horiz.</p>
<p>
he shows 64 by 64 array... good uniformity (using 300 mm process)</p>
<p>
good control of amplitude and the phase... perhaps can make holographic displays...</p>
<p>
compelling applic... 3d on cell phone...</p>
<p>
LIDAR (on chip scale)</p>
<p>
for autonomous vehicles.... everybody currently uses Velodyne LIDAR
which.. emits 64 beams vertically aligned and sweeps around...
(but these are extremely expensive)
his group is funded by toyota to do develop a phased array lidar that
would be attached at each corner of a car...
we've gotten to 51 degrees (but need 100 degrees to get overlap to get entire visual field)</p>
<p>
the phased array is much faster... 10 Khz.... (than the Velodyne)</p>
<p>
microwave photonics... another inter area...
tune with low loss (with heater)</p>
<p>
big potential to reduce power consump... (use SSB modulator)</p>
<p>
another app that could drive scaling...</p>
<p>
suspended SiN ring resonator... absorbs CO2 laser light at 10.6 micron...</p>
<p>
to use for sensing and imaging....
can get megapixel imager....</p>
<p>
today we are at 10K device level of integration on a chip (same as 1975 with CMOS)
will it scale to Ms and to Bs of elements (yes... at least to M elements)</p>
<p>
</p>