Nehalem (microarchitecture)
<p>Apr 19, 2008 6:43 PM
 
<b>Nehalem has the most significant new architectural changes as of 2008</b> since the <a href="/wiki/Pentium_Pro" title="Pentium Pro">Pentium Pro</a> back in <a href="/wiki/1995" title="1995">1995</a>. Nehalem is highly scalable<a href="#cite_note-4" title=""><sup class="reference" id="cite_ref-4">[5]</sup></a> with different components for different tasks. Various sources have stated that Nehalem's specifications will be as follows.</p>
<ul>
<li>1 through 8 (or more) cores.</li>
<li>Integrated <a href="/wiki/Memory_controller" title="Memory controller">memory controllers</a> supporting <a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3 SDRAM</a> and between 1 and 4 memory channels.</li>
<li>Manufactured using the same <a class="mw-redirect" href="/wiki/45_nm" title="45 nm">45 nm</a> manufacturing process as its predecessor, <i>Penryn</i>.</li>
<li>Some variants will have an integrated graphics processor (IGP) located off-die, but in the same CPU package.<a href="#cite_note-tech.co.uk-070919-5" title=""><sup class="reference" id="cite_ref-tech.co.uk-070919_5-0">[6]</sup></a></li>
</ul>
<ul>
<li>Some (if not all) variants will utilize the new point-to-point processor interconnect, the <a href="/wiki/Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">Intel QuickPath Interconnect</a>, replacing the legacy <a href="/wiki/Front_side_bus" title="Front side bus">front side bus</a>.</li>
<li><a class="mw-redirect" href="/wiki/Hyper-Threading" title="Hyper-Threading">HyperThreading</a>, which has not been present on a consumer Intel processor since 2006 with the <a href="/wiki/Pentium_4" title="Pentium 4">Pentium 4</a> and <a class="mw-redirect" href="/wiki/Pentium_EE" title="Pentium EE">Pentium EE</a>.</li>
<li>Native (monolithic, i.e. all processor cores on a single die) quad and octo (8) core processors.<a href="#cite_note-6" title=""><sup class="reference" id="cite_ref-6">[7]</sup></a></li>
<li>731 million transistors for the quad core variant.</li>
<li>32 KB L1 instruction and 32 KB L1 data cache per core.</li>
<li>256 KB L2 cache per core.</li>
<li>8 MB (in the quad core version) L3 cache shared by all CPU cores.</li>
<li>33% more in-flight micro-ops than Core.<a href="#cite_note-anandtech-Nehalem_Larrabee-7" title=""><sup class="reference" id="cite_ref-anandtech-Nehalem_Larrabee_7-0">[8]</sup></a></li>
<li>2nd level branch predictor and 2nd level Translation Lookaside Buffer.<a href="#cite_note-anandtech-Nehalem_Larrabee-7" title=""><sup class="reference" id="cite_ref-anandtech-Nehalem_Larrabee_7-1">[8]</sup></a></li>
<li>Modular blocks of components such as cores that can be added and subtracted for varying market segments.</li>
</ul>
<p> </p>