Common Platform Technology Forum 2013 GARY PATTON IBM
<p>Feb 10, 2013 09:30 PM
 
first hiK metal gate...
 
ARM  customer...
 
big investments in Samsung and GlobalFoundaries
 
1990s  planar CMOS...  better cost, better power... built the internet...
metal oxide at 3 atomic layers... could not do it...
 
Stressed oxides...
 
hiK metal gate...
 
new transition...  done with materials innovation so could say
 
3d devices and 3d chip-stacking...
 
bumps in the road:  LITHO!  Num Aperture... must extend immersion
interconnects....   RC delays are a killer....
 
atomic dimension regime...  III/V devices  CNTs....
 
FinFET device  epitaxial devices at 2 nm...
 
silicon or nanowiring. coming....
 
optimize the entire stack...
 
EDA suppliers
 
Watson... used  Power 7 our proces chip  567 mm2...  80MB  RAM memory..
 
partner ARM  and EDA suppliers...
 
 
CNT
 wearable electrnics  flexible layer of material
fd SOI...    
 
sci fiction era...  full flexible dispalys...
implanted into body...
 
York, Albany and Zurich... 3 r and d center  of IBM... most patents of any company in the world.
 
EUV center of competency... in Albany
 
Sematech... eqpt and suppliers  in Albany...
 
LITHO is at the foundation... everything depends on that
 
k1 factor  higher is better...
 
immersion first at 45 nm...
 
at 20 and 14 need to go to dbl and triple
 
big bump in k1 factor if we can get EUV...
 
2 exposures... not so great
 
EUV high vacuum...  reflective lenses and masks... lots challenges...
 
30 watts  power  now... need to  get to 250 watts...
Must get there... he chuckles...
 
cannot use a pellicle... must be completely defect free...
 
6 mirrors... effic is only 6% each....
 
real physics problems!! (not just engr)  our best physicists working on this....
 
must hit same 1 inch
 
inspect 10% of California and make sure there are no golfballs in that area  (defectivity!!!)...
 
but working with   Cymer... tool in April
 
will not be ready for 14 or 10!!!!!  but may be for 7...
 
flexible light source for  immersion...  (we've been working on EUV etc for > 10 years)
 
 
Dbl patterning:  split the mask into 2 parts each at 2 pitch...   must align them
but at pitch.. interspersed......pink, blu, pink blu...
 
but have jogs and jags... v hard to do this...  conflicts...  but v hard to do this...
 
10 nm  how to dbl pattern...
 
sidewall limit transfer... (use the sidewalls of each line to dbl the freq of lines...
 
at 7nm  triple and quad patterning... v expensive....
 
use chemistry... block copolymers... like oil and water...  align in alternating patterns...
determined by copolymer...  align as ABABAB patterns...  remove  Bs  etc
use dbl  and get results of dbl patterning....
 
end of planara... in the era of  fd SOI...
 
silicon nanowires... but them
 
CNT or 3/5 devices....
 
fdSOI...   source and drain get close to ... fully depelete so that there is no leakage..
 
Fin FET  wrap around gate... footprint is not determinative....
 
but existing Fin FETS have variability....  strong device at top and poor at bottom...
want very veritcal to get the fill with dielectric......
 
smaller Fins...  get more variability....
 
Fin doping...  gotten a 2x improvement...
 
CNTs...   instead of Fins....   CNT   great transport properties...
2 challenges...   30% are metallic (of CNTs)...  use chromatography to separate these from semiconducs
steady progress to get these...
 
placement:   slective bond to hafnium oxide... we have put a billion... circuits as a big as 10,000!
major breakthru...
 
interconnects....   resistance goes way up with diameter...
wire capac.  vs dielectric constant...
RC delay in interconnects...  see it at 24 nm  (with 64 nm pitch)
 
wire lifetime with scalability...  higher fields, small they electromigrate...
get voids and seams...
 
reliability...  tbdb ( breakdown...   move into redzone at give dielectric constant...
avoid seams and voids; 
 
photonics will give us a huge improvement...
he shows modulators...  control nanophotonic waveguide... how to integrate...
adjacent to  CMOS circuit....  25 Gbit/sec
 
ultimate:  3d and photonoics...  memory plane, logic plane, photonics...
logic plane next to    300 cores...  1 terabyte per sec...
 
CMOS sclaing will continue
CNT and silicon photonics...
 
 
 
 
 
 
 
 
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